1. Field of the Invention
This invention relates to microcoded instructions, and particularly to systems, methods and computer program products for hardware assists for microcoded floating point divide and square root operations.
2. Description of Background
The A2 core is a four threaded processor. While most instructions are executed using dedicated hardware, the floating point divide (fdiv(s)(.)) and square root (fsqrt(s)(.)) instructions are microcoded. Whenever a microcoded instruction is decoded, a signal is sent out to abort the instruction and all instructions following it in the pipeline. The same signal also starts the execution of the microcode routine for the microcoded instruction. A streamlined microcode sequence that handles the majority of operands for division or square root can be written with about 12 instructions. Handling all possible operands requires branches in the microcode and adds many more instructions to the main line code. Branching on various floating point operand classifications can be difficult. For example, the operand(s) would need to be copied from the floating point architectural registers (FPR(s)) to the general purpose registers (GPR(s)), requiring GPR(s) to first be saved and later restored. Alternatively, a new Floating point operation that examines an FPR and writes results into a register in the Instruction Issue Unit would need to be constructed. The microcode would need to branch based on the contents of this new register (i.e., detect read-after-write (RAW) dependency). Currently, the microcode engine of A2 processor does not support any branching.